Error Correction In Flash Memory Devices
Flash memory devices have been known for many years. NAND-type flash memories differ from other types of flash memories (e.g. NOR-type), among other characteristics, by the fact that a certain number of information bits, written to the memory, may be read from the memory in a “flipped” state (i.e. different from the state that the original bits were written to the memory).
In order to overcome this phenomenon and to make NAND-type memories usable by real applications, it is a common technique to use Error Correction Codes (ECC) in conjunction with these memories.
There is an ongoing need for improved techniques and apparatus for handling error correction in flash memory devices, and in storage devices that include memory other than flash memory.
A Discussion of Exemplary Device Architecture
FIG. 1A (prior art) is a block diagram of a flash memory storage device 260 (prior art). The flash memory storage device includes a flash memory 270 and a flash controller 280 operative to read data and to write data to the flash memory 270. The terms “program”, “programming”, “programmed”, and “programmable” are used herein interchangeably with the terms “write”, “writing”, “written”, and “writable”, respectively, to denote the storing of data in a flash memory.
One example of a flash memory storage device is a “peripheral flash storage device.” Peripheral flash storage devices are well-known in the art of computing, in form factors such as USB flash drives (UFD); PC-cards; and small storage cards used with digital cameras, music players, handheld and palmtop computers, and cellular telephones.
In some implementations, the peripheral flash storage device is deployed within a housing of the host device.
FIG. 1B (prior art) is a block diagram of a peripheral flash memory storage device 260* (the asterisk indicates that the flash memory storage device is a peripheral flash storage device) that is “coupled with” or configured to exchange data with a host device 310 (for example, a laptop or desktop or handheld computers, digital camera, mobile telephone, music player, and video game consoles) via device-side interface 250. Peripheral flash memory storage device 260* and host device 310 communicate with each other via communications link 300 using host-side interface 350 and device-side interface 250 (for example, respective USB or SD interfaces).
In one example, flash memory storage device 260* provides data-reading and data-writing services to host device 310. Data received by flash memory storage device 260* from host device 310 is written to flash memory 270 by flash controller 280. Furthermore, in response to “data read” requests received by flash memory storage, flash controller 280 reads data from flash memory 270.
Errors may be corrected in the read data at “read time” or at any later time. The error-correction may be carried out at least in part by flash controller 280, at least in part by host device 310 (for example, by execution of executable code 340 in RAM 330 by host-side processor 320 or in any other manner), and any other location and in any other manner.
The skilled artisan will appreciate that “peripheral flash storage devices” are not the only class of flash memory storage devices. For example, certain mobile phones, desktop or laptop computers, PDA devices or other electronic devices may also include flash memory and a flash controller, and may not necessarily be configured to couple with a host device and/or provide data reading services and/or data writing service for a host device.
The skilled artisan will appreciate that the flash memory devices described in FIGS. 1A-1B are just one class of peripheral storage memory device, and other memory devices may include other types of volatile memory, such as magnetic memory (for example, magnetoresistive random-access memory (MRAM) or hard disk platters). Furthermore, it is appreciated that the some peripheral storage devices may use volatile memory instead of, or in addition to, flash memory 270.
As illustrated in FIG. 1C (prior art), in some systems, a memory (i.e. including but not limited to a flash memory) may include a ‘cache storage region 272’ and a ‘main storage region 274’ portion where data is first written to the ‘cache storage region 272’ (for example, copied from RAM of a flash device controller 280 to the cache storage region 272 of flash memory) and is subsequently copied from the cache storage region 272 to the main storage region 274.
In many examples, (i) the cache storage region 272 is written to using a ‘faster writing mode’ than a writing mode used for main storage region 274; and/or (ii) the main storage region 274 is larger (i.e. has a greater capacity) than the cache storage region 272; and/or (iii) the data stored to the cache storage region 272 is stored with a greater degree of reliability (i.e. and is less prone to errors at programming time and/or subsequent to programming time) than the data stored to the main storage region 274.
In one particular example, the ‘cache storage region 272 includes flash blocks where N bits of data are stored in each flash cell where N is a positive integer, and the main storage region 274 includes flash blocks where M bits of data are stored in each flash cell where M is a positive integer that exceeds N.